Bio

I’m an EE PhD candidate at Stanford University supervised by Prof. H.-S. Philip Wong, while working closely with Prof. Priyanka Raina and Prof. Subhasish Mitra. I also collaborate with Prof. Jan M. Rabaey at UC Berkeley. My research theme is centered around energy-efficient machine learning systems enabled by emerging nanotechnologies (e.g., 3D resistive memories). To support my vision of future intelligent nanosystems, my technical efforts span from experimental studies and device-to-system modeling, to efficient architectures and their chip implementations.

I have published more than 30 papers appearing in important conferences (IEDM, ISSCC, VLSI, DAC) and journals (JSSC, Nature Electronics), including several invited papers. Together with my colleagues, our research has been covered by EE Times, Forbes, Storage Newsletter, Stanford News. Meanwhile, I serve as an active reviewer for JSSC, Scientific Reports, EDL, T-ED, Applied Physics Letters, T-CAD, T-VLSI, and several IEEE conferences.

I’m a recipient of 2016 IEEE EDS Masters Student Fellowship, Best Paper Award at 2016 SRC TECHCON, ‘Golden List of Reviewers’ by IEEE EDL and T-ED, and nomination for Best Student Paper Award at 2016 Symposium of VLSI Technology.